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F49L160UA/F49L160BA 16 Mbit (2M x 8/1M x 16) 3V Only CMOS Flash Memory
1. FEATURES
Single supply voltage 2.7V-3.6V Fast access time: 70/90 ns 2,097,152x8 / 1,048,576x16 switchable by BYTE pin Compatible with JEDEC standard - Pin-out, packages and software commands compatible with single-power supply Flash Low power consumption - 7mA typical active current - 25uA typical standby current 100,000 program/erase cycles typically 20 Years Data Retention Command register architecture - Byte Word Programming (9s/11s typical) - Byte Mode : One 16KB, two 8KB, one 32KB, and thirty-one 64KB sectors. - Word Mode : one 8K word, two 4K word, one 16K word, and thirty-one 32 K word sectors. Auto Erase (chip & sector) and Auto Program - Any combination of sectors can be erased concurrently; Chip erase also provided. - Automatically program and verify data at specified address Erase Suspend/Erase Resume - Suspend or Resume erasing sectors to allow the read/program in another sector Ready/Busy (RY/ BY ) - RY/ BY output pin for detection of program or erase operation completion End of program or erase detection - Data polling - Toggle bits Hardware reset - Hardware pin( RESET ) resets the internal state machine to the read mode Sector Protection /Unprotection - Hardware Protect/Unprotect any combination of sectors from a program or erase operation. Low VCC Write inhibit is equal to or less than 2.0V Boot Sector Architecture - U = Upper Boot Block - B = Bottom Boot Block Packages available: - 48-pin TSOPI CFI (Common Flash Interface) complaint - Provides device-specific information to the system, allowing host software to easily reconfigure to different Flash devices.
2. ORDERING INFORMATION
Part No F49L160UA-70T F49L160BA-70T Boot Upper Bottom Speed 70 ns 70 ns Package TSOPI TSOPI Part No F49L160UA-90T F49L160BA-90T Boot Upper Bottom Speed 90 ns 90 ns Package TSOPI TSOPI
3. GENERAL DESCRIPTION
The F49L160UA/F49L160BA is a 16 Megabit, 3V only CMOS Flash memory device organized as 2M bytes of 8 bits or 1M words of 16bits. This device is packaged in standard 48-pin TSOP. It is designed to be programmed and erased both in system and can in standard EPROM programmers. With access times of 70 ns and 90 ns, the F49L160UA/F49L160BA allows the operation of high-speed microprocessors. The device has separate chip enable CE , write enable WE , and output enable OE controls. EFST's memory devices reliably store memory data even after 100,000 program and erase cycles. The F49L160UA/F49L160BA is entirely pin and command set compatible with the JEDEC standard for 16 Megabit Flash memory devices. Commands are written to the command register using standard microprocessor write timings. The F49L160UA/F49L160BA features a sector erase architecture. The device array is divided into one 16KB, two 8KB, one 32KB, and thirty-one 64KB for byte mode. The device memory array is divided into one 8K word, two 4K word, one 16K word, and thirty-one 32K word sectors for word mode. Sectors can be erased individually or in groups without affecting the data in other sectors. Multiple-sector erase and whole chip erase capabilities provide the flexibility to revise the data in the device. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory. This can be achieved in-system or via programming equipment. A low VCC detector inhibits write operations on loss of power. End of program or erase is detected by the Ready/Busy status pin, Data Polling of DQ7, or by the Toggle Bit I feature on DQ6. Once the program or erase cycle has been successfully completed, the device internally resets to the Read mode.
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4. PIN CONFIGURATIONS 4.1 48-pin TSOP
F49L160UA/F49L160BA
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE RES ET NC NC RY/ BY A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BY TE GND DQ15/A -1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE GND CE A0
F49L160U/BA
4.2
Pin Description
Symbol Pin Name Address Input Data Input/Output Q15 (Word mode) / LSB addr (Byte Mode) Chip Enable Output Enable Write Enable Reset Word/Byte selection input Ready/Busy Power Supply Ground No connection Functions To provide memory addresses. To output data when Read and receive data when Write. The outputs are in tri-state when OE or CE is high. To bi-direction date I/O when BYTE is High To input address when BYTE is Low To activate the device when CE is low. To gate the data output buffers. To control the Write operations. Hardware Reset Pin/Sector Protect Unprotect To select word mode or byte mode To check device operation status To provide power
A0~A19 DQ0~DQ14 DQ15/A-1 CE OE
WE
RESET
BYTE
RY/ BY VCC GND NC
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5. SECTOR STRUCTURE
F49L160UA/F49L160BA
Table 1: F49L160UA Sector Address Table Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 Sector Size Byte Mode 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 32Kbytes 8Kbytes 8Kbytes 16Kbytes Word Mode 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 16Kwords 4Kwords 4Kwords 8Kwords Address range Byte Mode(x8) 000000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1F7FFF 1F8000-1F9FFF 1FA000-1FBFFF 1FC000-1FFFFF 00000-07FFF 08000-0FFFF 10000-17FFF 18000-1FFFF 20000-27FFF 28000-2FFFF 30000-37FFF 38000-3FFFF 40000-47FFF 48000-4FFFF 50000-57FFF 58000-5FFFF 60000-67FFF 68000-6FFFF 70000-77FFF 78000-7FFFF 80000-87FFF 88000-8FFFF 90000-97FFF 98000-9FFFF A0000-A7FFF A8000-AFFFF B0000-B7FFF B8000-BFFF C0000-C7FFF C8000-CFFFF D0000-D7FFF D8000-DFFFF E0000-E7FFF E8000-EFFFF F0000-F7FFF F8000-FBFFF FC000-FCFFF FD000-FDFFF FE000-FFFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 Sector Address 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X Word Mode(x16) A19 A18 A17 A16 A15 A14 A13 A12
Note: Byte Mode: address range A19 : A-1, Word mode : address range A19 : A0
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Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 Sector Size Byte Mode 16Kbytes 8Kbytes 8Kbytes 32Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes 64Kbytes Word Mode 8Kwords 4Kwords 4Kwords 16Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords 32Kwords Address range Byte Mode(x8) 000000-003FFF 004000-005FFF 006000-007FFF 008000-008FFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1FFFFF
F49L160UA/F49L160BA
Table 2: F49L160BA Sector Address Table Sector Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Word Mode(x16) A19 A18 A17 A16 A15 A14 A13 A12 00000-01FFF 02000-02FFF 03000-03FFF 04000-07FFF 08000-0FFFF 10000-17FFF 18000-1FFFF 20000-27FFF 28000-2FFFF 30000-37FFF 38000-3FFFF 40000-47FFF 48000-4FFFF 50000-57FFF 58000-5FFFF 60000-67FFF 68000-6FFFF 70000-77FFF 78000-7FFFF 80000-87FFF 88000-8FFFF 90000-97FFF 98000-9FFFF A0000-A7FFF A8000-AFFFF B0000-B7FFF B8000-BFFFF C0000-C7FFF C8000-CFFFF D0000-D7FFF D8000-DFFFF E0000-E7FFF E8000-EFFFF F0000-F7FFF F8000-FFFFF
Note: Byte Mode: address range A19 : A-1, Word mode : address range A19 : A0
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6. FUNCTIONAL BLOCK DIAGRAM
F49L160UA/F49L160BA
BYTE CE OE WE RES ET CONTROL INPUT LOGIC PROGRAM / ERASE HIGH VOLTAGE WRITE STATE MACHING (WSM)
STATE REGISTER
F49L400U/BA
A0~A19
ADDRESS LATCH AND BUFFER
FLASH ARRAY
ARRAY SOURCE HV
Y-PASS GATE
COMMAND DATA DECODER
SENSE AMPLIFIER
PGM DATA HV
COMMAND DATA LATCH
PROGRAM DATA LATCH
DQ0~DQ14 DQ15 / A-1
I / O BUFFER
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7. FUNCTIONAL DESCRIPTION 7.1 Device operation
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The register is composed of latches that store the command, address and data information needed to execute the command. The contents of the
F49L160UA/F49L160BA
register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The F49L160UA /F49L160BA features various bus operations as Table 3.
Table 3. F49L160UA/F49L160BA Operation Modes Selection ADDRESS DESCRIPTION
CE
OE
DQ8~DQ15
WE
RESET
A19 A11 A8 A5 DQ0~DQ7 | | | | A9 A6 A1 A0 A12 A10 A7 A2
BYTE
=VIH
BYTE
=VIL
Reset(3) Read Write Output Disable Standby Sector Protect(2) Sector Unprotect(2)
Temporary sector unprotect
X L L L VCC 0.3V L L X
X L H H X H H X
X H L H X L L X
L, Vss 0.3V(3) H H H VCC 0.3V VID VID VID SA SA X X X X X X
X AIN AIN X X L H X X H H L L
High Z Dout DIN High Z High Z DIN DIN DIN
High Z Dout DIN High Z High Z X X DIN
High Z
DQ8~DQ14=
High Z DQ15=A-1 High Z High Z X X High Z
AIN See Table 4
Auto-select Notes:
1. L= Logic Low = VIL, H= Logic High = VIH, X= Don't Care, SA= Sector Address, VID=10V to 10.5V.
AIN= Address In, DIN = Data In, Dout = Data Out. 2. The sector protect and unprotect functions may also be implemented via programming equipment. 3. See "Reset Mode" section.
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Description Mode
CE OE
WE
F49L160UA/F49L160BA
Table 4. F49L160UA/F49L160BA Auto-Select Mode (High Voltage Method) A19 A11 to to A12 A10 A9 A8 to A7 A6 X X L L A5 to A2 X X A1 L L A0 L H DQ8 to DQ15 X 22H X X X VID X L X L H 22H X SA X VID X L X H L X X DQ7 to DQ0 7FH C4H C4H 49H 49H 01H (protected) 00H (unprotected)
Manufacturer ID: EFST
Device ID: F49L160UA (Upper Boot Block) Device ID: F49L160BA (Bottom Boot Block)
L L L L L L
L L L L L L
H H H H H H
X X
X X
VID VID
Word Byte Word Byte
Sector Protection Verification
L= Logic Low=VIL, H= Logic High=VIH, SA= Sector Address, X= Don't care. Notes : 1.Manufacturer and device codes may also be accessed via the software command sequence in Table 5.
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Reset Mode : Hardware Reset
When the RESET pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tri-states all output pins, and ignores all read/write commands for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated later once the device is ready to accept another command sequence, to ensure the data integrity. The current is reduced for the duration of the RESET pulse. When RESET is held at VSS0.3V, the device draws CMOS standby current (ICC4). If RESET is held at VIL but not within VSS0.3V, the standby current will be greater. The RESET pin may be tied to system reset circuitry. A system reset would thus reset the Flash memory, enabling the system to read the boot-up firm-ware from the Flash memory. If RESET is asserted during a program or erase embedded algorithm operation, the RY/ BY pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/ BY to determine whether the reset operation is complete. If RESET is asserted when a program or erase operation is not executing , i.e. the RY/ BY is "1", the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data after tRH when the RESET pin returns to VIH. Refer to the AC Characteristics tables 17 for Hardware Reset section & Figure 23 for the timing diagram.
F49L160UA/F49L160BA
valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Read Command" section for more information. Refer to the AC Read Operations table 14 for timing specifications and to Figure 5 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data.
Write Mode
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE and CE to VIL, and OE to VIH. The "Program Command" section has details on programming data to the device using standard command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Tables 1 and 2 indicate the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Software Command Definitions" section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. When the system writes the auto-select command sequence, the device enters the auto-select mode. The system can then read auto-select codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the Auto-select Mode and Auto-select Command sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain unchanged for over 250ns. The automatic sleep mode is independent of the CE , WE , and OE control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification.
Read Mode
To read array data from the outputs, the system must drive the CE and OE pins to VIL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor's read cycles that assert
Word / Byte Mode
This pin control the I/O configuration of device. When
BYTE = VIH or Vcc 0.3V. The I/O configuration is x16 and the pin of D15/A-1 is bi-direction Data I/O. However, BYTE = VIL or VSS 0.3V. The I/O configuration would be x8 and The pin of DQ15/A-1 only address input pin. You must define the function of this pin before enable this device.
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Temporary Sector Unprotect Mode
This feature allows temporary unprotection of previously protected sector to change data in-system. This mode is activated by setting the RESET pin to VID(10V-10.5V). During this mode, all formerly protected sectors are
F49L160UA/F49L160BA
un-protected and can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET pin, all the previously protected sectors are protected again.
Start
RESET = VID (Note 1)
Perform Erase or Program Operation
Operation Completed
RESET = VIH
Temporary Sector Unprotect Completed (Note 2)
Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again.
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Output Disable Mode
With the OE is at a logic high level (VIH), outputs from the devices are disabled. This will cause the output pins in a high impedance state
F49L160UA/F49L160BA
Figure 16 shows the algorithms and Figure 15 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires VID on address pin A9, OE , and RESET .
Standby Mode
When CE and RESET are both held at VCC 0.3V, the device enter CMOS Standby mode. If CE and
RESET are held at VIH, but not within the range of VCC 0.3V, the device will still be in the standby mode, but the standby current will be larger.
Auto-select Mode
The auto-select mode provides manufacturer and device identification and sector protection verification, through outputs on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the auto-select codes can also be accessed in-system through the command register. When using programming equipment, this mode requires VID (10 V to 10.5 V) on address pin A9. While address pins A3, A2, A1, and A0 must be as shown in Table 4. To verify sector protection, all necessary pins have to be set as required in Table 4, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the auto-select codes in-system, the host system can issue the auto-select command via the command register, as shown in Table 5. This method does not require VID. See " Software Command Definitions" for details on using the auto-select mode.
If the device is deselected during auto algorithm of erasure or programming, the device draws active current ICC2 until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. The device requires standard access time (tCE) for read access from either of these standby modes, before it is ready to read data.
Sector Protect / Un-protect Mode
The hardware sector protect feature disables both program and erase operations in any sector. The hardware sector unprotect feature re-enables both the program and erase operations in previously protected sectors. Sector protect/unprotect can be implemented via two methods. The primary method requires VID on the RESET pin only, and can be implemented either in-system or via programming equipment.
7.2 Software Command Definitions
Writing specific address and data commands or sequences into the command register initiates the device operations. Table 5 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE or CE , whichever happens later. All data is latched on the rising edge of WE or CE , whichever happens first. Refer to the corresponding timing diagrams in the AC Characteristics section.
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Command Reset (5) Read (4) Program Word Byte Word Byte Word Byte Bus Cycles 1 1 4 4 6 6 6 6 1 1 1st Bus Cycle Addr XXXH RA 555H Data F0H RD AAH 2nd Bus Cycle Addr 2AAH 555H 2AAH 555H 2AAH 555H Data 55H 55H 55H 55H 55H 55H 3rd Bus Cycle Addr 555H AAAH 555H AAAH 555H AAAH Data A0H A0H 80H 80H 80H 80H -
F49L160UA/F49L160BA
Table 5. F49L160UA/F49L160BA Software Command Definitions 4th Bus Cycle Addr PA PA 555H Data PD PD AAH 2AAH 555H 2AAH 555H 55H 55H 55H 55H 555H AAAH SA SA 10H 10H 30H 30H 5th Bus Cycle Addr Data 6th Bus Cycle Addr Data -
AAAH AAH 555H AAH
Chip Erase
AAAH AAH 555H AAH
AAAH AAH 555H AAH
Sector Erase Sector Erase Suspend (6)
AAAH AAH XXXH XXXH B0H 30H
AAAH AAH -
Sector Erase Resume (7) Auto-select Notes:
See Table 6.
1. X = don't care RA = Address of memory location to be read. RD = Data to be read at location RA. PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address of the sector. 2. Except Read command and Auto-select command, all command bus cycles are write operations. 3. The system should generate the following address patterns: 555H or 2AAH to address A10~A0 in word mode / AAAH or 555H to address A10~A-1 in byte mode. 4. Address bits A19-A11 are don't cares. 5. No command cycles required when reading array data. 6. The Reset command is required to return to reading array data when device is in the auto-select mode, or if DQ5 goes high(while the device is providing status data). 7. The system may read and program in non-erasing sectors, or enter the auto-select mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 8. The Erase Resume command is valid only during the Erase Suspend mode.
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Bus Cycles 4 Manufacture ID 4 4 4 Device ID, Upper boot Device ID, Bottom boot Word Byte Word Byte Word
Sector Protect Verify
F49L160UA/F49L160BA
Table 6. F49L160UA/F49L160BA Auto-Select Command 1st Bus Cycle Addr 555H 555H 555H 555H 555H 2nd Bus Cycle Data 55H 55H 55H 55H 55H 55H 55H 55H 55H 3rd Bus Cycle Addr 555H 555H 555H 555H 555H AAAH 555H AAAH 555H Data 90H 90H 90H 90H 90H 90H 90H 90H 90H 4th Bus Cycle Addr X04H X08H X0CH X00H Data 7FH 7FH 7FH 8CH 5th Bus Cycle 6th Bus Cycle
Command
Data Addr AAH 2AAH AAH 2AAH AAH 2AAH AAH 2AAH AAH 2AAH
Addr Data Addr Data -
4 4 4 4 4
X01H 22C4H X02H C4H
AAAH AAH 555H 555H AAH 2AAH
X01H 2249H X02H 49H
-
-
-
-
AAAH AAH 555H 555H AAH 2AAH
(SA) XX00H x02H XX00H (SA) x04H 00H 01H
-
-
-
-
Byte
4
AAAH AAH 555H
55H
AAAH
90H
Notes :
1. The fourth cycle of the auto-select command sequence is a read cycle.
2.
For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H, it means the sector is still not being protected.
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Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are all don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an auto-select command sequence. Once in the auto-select mode, the reset command must be written to return to reading array data (also applies to auto-select during Erase Suspend). If DQ5 goes high(see "DQ5: Exceeded Timing Limits" section) during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).
F49L160UA/F49L160BA
Program Command
The program command sequence programs one byte into the device. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/ BY . See "Write Operation Status" section for more information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set DQ5 to "1", or cause the Data Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1".
Read Command
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. When the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the auto-select mode. See the "Reset Command" section. See also the "Read Mode" in the "Device Operations" section for more information. Refer to Figure 5 for the timing diagram.
Chip Erase Command
Chip erase is a six-bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure the data integrity.
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The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/ BY . See "Write Operation Status" section for more information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. See the Erase/Program Operations tables in "AC Characteristics" for parameters.
F49L160UA/F49L160BA
operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure the data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/ BY . (Refer to "Write Operation Status" section for more information on these status bits.) Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters.
Sector Erase Command
Sector erase is a six-bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the "DQ3: Sector Erase Timer" section.) The time-out begins from the rising edge of the final WE pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the
Sector Erase Suspend/Resume Command
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure (The device "erase suspends" all sectors selected for erasure.). This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Addresses are "don't-cares" when writing the Erase Suspend command as shown in Table 5. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Reading at any address within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See "Write Operation Status" section for more information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The system may also write the auto-select command sequence when the device is in the Erase Suspend mode. The device allows reading auto-select codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the auto-select mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation.
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The system must write the Erase Resume command (address bits are "don't care" as shown in Table 5) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.
F49L160UA/F49L160BA
The auto-select command sequence is initiated by writing two unlock cycles, followed by the auto-select command. The device then enters the auto-select mode, and the system may read at any address any number of times, without initiating another command sequence. The read cycles at address 04H, 08H, 0CH, and 00H retrieves the EFST manufacturer ID. A read cycle at address 01H retrieves the device ID. A read cycle containing a sector address (SA) and the address 02H returns 01H if that sector is protected, or 00H if it is unprotected. Refer to Tables 1 and 2 for valid sector addresses. The system must write the reset command to exit the auto-select mode and return to reading array data.
Auto-select Command
The auto-select command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 6 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires VID on address bit A9.
7.3 Write Operation Status
The device provides several bits to determine the status of a write operation: RY/ BY , DQ7, DQ6, DQ5, DQ3, DQ2, and. Table 7 and the following subsections describe the functions of these bits. RY/ BY , DQ7, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress.
Table 7. Write Operation Status Status Embedded Program Algorithm Embedded Erase Algorithm In Progress Reading Erase Suspended Sector Erase Suspended Mode Reading Non-Erase Suspended Sector Erase Suspend Program Embedded Program Algorithm Exceeded Time Limits Embedded Erase Algorithm Erase Suspend Program Notes: 1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 2. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See "DQ5: Exceeded Timing Limits" for more information. DQ7 (Note1)
DQ7
DQ6 Toggle Toggle No Toggle Data Toggle Toggle Toggle Toggle
DQ5 DQ3 (Note2) 0 0 0 Data 0 1 1 1 N/A 1 N/A Data N/A N/A 1 N/A
DQ2 No Toggle Toggle Toggle Data N/A No Toggle Toggle N/A
RY/ BY 0 0 1 1 0 0 0 0
0 1 Data
DQ7
DQ7
0
DQ7
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RY/ BY : Ready/Busy
The RY/ BY is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/ BY status is valid after the rising edge of the final WE pulse in the command sequence. Since RY/ BY is an open-drain output, several RY/ BY pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 7 shows the outputs for RY/ BY .
F49L160UA/F49L160BA
Output Enable ( OE ) is asserted low. Refer to Figure 21, Data Polling Timings (During Embedded Algorithms), Figure 19 shows the Data Polling algorithm.
DQ6:Toggle BIT I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE or CE to control the read cycles. When the operation is complete, DQ6 stops toggling. When an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (i.e. the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7. If a program address falls within a protected sector, DQ6 toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 7 shows the outputs for Toggle Bit I on DQ6. Figure 20 shows the toggle bit algorithm. Figure 22 shows the toggle bit timing diagrams. Figure 25 shows the differences between DQ2 and DQ6 in graphical form. Refer to the subsection on DQ2: Toggle Bit II.
DQ7: Data Polling
The DQ7 indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend mode. The Data Polling is valid after the rising edge of the final WE pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the true data on DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 s, then the device returns to reading array data. During the Embedded Erase algorithm, Data Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7~ DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0-DQ6 while
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE or CE , whichever happens first, in the command sequence.
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DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE or CE to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or whether is in erase-suspended, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 7 to compare outputs for DQ2 and DQ6. Figure 20 shows the toggle bit algorithm in flowchart form. See also the DQ6: Toggle Bit I subsection. Figure 22 shows the toggle bit timing diagram. Figure 25 shows the differences between DQ2 and DQ6 in graphical form.
F49L160UA/F49L160BA
exceeded the specified limits(internal pulse count). Under these conditions DQ5 will produce a "1". This time-out condition indicates that the program or erase cycle was not successfully completed. Data Polling and Toggle Bit are the only operating functions of the device under this condition. If this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for the program or erase operation. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute program or erase command sequence. This allows the system to continue to use the other active sectors in the device. If this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this time-out condition occurs during the programming operation, it specifies that the sector containing that byte is bad and this sector may not be reused, however other sectors are still functional and can be reused. The time-out condition will not appear if a user tries to program a non blank location without erasing. Please note that this is not a device failure condition since the device was incorrectly used.
Reading Toggle Bits DQ6/ DQ2
Refer to Figure 20 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described earlier. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation.
DQ3:Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from "0" to "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. When the sector erase command sequence is written, the system should read the status on DQ7 (Data Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is "1", the internally controlled erase cycle has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0", the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 7 shows the outputs for DQ3.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
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7.4 More Device Operations
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
F49L160UA/F49L160BA
Write cycles are inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle, CE and WE must be a logical zero while OE is a logical one.
Power Supply Decoupling
In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected between its VCC and GND.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Power-Up Sequence
The device powers up in the Read Mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences.
Power-Up Write Inhibit
If WE = CE = VIL and OE = VIH during power up, the device does not accept commands on the rising edge of WE . The internal state machine is automatically reset to reading array data on power-up.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on CE or WE do not initiate a write cycle.
Logical Inhibit
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COMMON FLASH MEMORY INTERFACE (CFI)
F49L160UA/F49L160BA
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward- compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to array data. The system can read CFI information at the address given in Tables 8-10 in word mode, the upper address bits (A7-MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the devices is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 8-10. The system must write the reset command to return the device to the autoselect mode.
Table 8 CFI Query Identification String
Addresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Address (Byte Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description
Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
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Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Address (Byte Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h
F49L160UA/F49L160BA
Table 9 System Interface String
Description VCC Min. (write/erase) D7~D4 : volt, D3~D0 : 100 millivolt VCC Max. (write/erase) D7~D4 : volt, D3~D0 : 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present)
N Typical timeout per single byte/word write 2 s
Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N word times typical Max. timeout for buffer write 2N word times typical Max. timeout per individual block erase 2N word times typical Max. timeout per full chip erase 2N word times typical (00h = not supported)
Table 10 Device Geometry Definition
Addresses (Word Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Address (Byte Mode) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h Data 0015h 0002h 0000h 0000h 0000h 0004h 0000h 0000h 0004h 0000h 0001h 0000h 0020h 0000h 0000h 0000h 0080h 0000h 001Eh 0000h 0000h 0001h Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Description
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
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Addresses (Word Mode) 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch Address (Byte Mode) 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h 92h 94h 96h 98h Data 0050h 0052h 0049h 0031h 0030h 0000h 0002h 0001h 0001h 0004h 0000h 0000h 0000h
F49L160UA/F49L160BA
Table 11 Primary Vendor-Specific Extended Query
Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0 = Required, 1 = Not Required Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Erase Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800A mode Simultaneous Operation 00 = Not Supported, 01 = Supported Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
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8. ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . .. . . . . . -65C to +125C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . .-0.5 V to +4.0 V A9, OE , and RESET (Note 2) .... . . .. . . . . -0.5 V to +12.5 V All other pins (Note 1). . . . . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) .. . .. 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 1. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 2.
F49L160UA/F49L160BA
2. Minimum DC input voltage on pins A9, OE , and RESET is -0.5 V. During voltage transitions, A9, OE , and RESET may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 1. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1. Maximum Negative Overshoot Waveform
20 n s +0.8V -0.5V -2.0V 20 n s 20 n s
Figure 2. Maximum Positive Overshoot Waveform
20 n s Vc c +2.0V Vc c +0.5V 2.0V 20 n s 20 n s
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OPERATING RANGES
F49L160UA/F49L160BA
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . 0C to +70C VCC Supply Voltages VCC for all devices . . . . . . . . . . . . . . . . . . . . .2.7 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. Table 12. Capacitance TA = 25C , f = 1.0 MHz Symbol CIN1 CIN2 COUT Description Input Capacitance Control Pin Capacitance Output Capacitance Conditions VIN = 0V VIN = 0V VOUT = 0V Min. Typ. Max. 8 12 12 Unit pF pF pF
9. DC CHARACTERISTICS
Table 13. DC Characteristics TA = 0C to 70C, VCC = 2.7V to 3.6V Symbol ILI ILIT ILO Description Input Leakage Current A9 Input Leakage Current Output Leakage Current Conditions VIN = VSS or VCC, VCC = VCC max. VCC = VCC max; A9=12.5V VOUT = VSS or VCC, VCC = VCC max
CE = VIL, OE = VIH ( Byte Mode ) CE = VIL, OE = VIH ( Word Mode )
Min.
Typ.
Max. 1 35 1
Unit uA uA uA mA mA mA mA mA uA uA uA V V V V
@5MHz @1MHz @5MHz @1MHz
9 2 9 2 20 0.2 0.2 0.2 -0.5 0.7x VCC
16 4 16 4 30 5 5 5 0.8 VCC + 0.3 10.5 0.45
ICC1
VCC Active Read Current
ICC2 ICC3 ICC4 ICC5 VIL VIH VID VOL VOH1 VOH2 VLKO Notes :
VCC Active write Current VCC Standby Current VCC Standby Current During Reset Automatic sleep mode Input Low Voltage(Note 1) Input High Voltage Voltage for Auto-Select and Temporary Sector Unprotect Output Low Voltage Output High Voltage(TTL) Output High Voltage Low VCC Lock-out Voltage
CE = VIL, OE = VIH CE ; RESET = VCC 0.3V RESET = VSS 0.3V
VIH = VCC 0.3V; VIL = VSS 0.3V
VCC =3.3V IOL = 4.0mA, VCC = VCC min IOH = -2mA, VCC = VCC min IOH = -100uA, VCC min
10
0.7x VCC VCC -0.4 2.3 2.5 V
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns. VIL min. = -2.0V for pulse width is equal to or less than 20 ns. 2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns If VIH is over the specified maximum value, read operation cannot be guaranteed. 3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC + 30 ns
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10. AC CHARACTERISTICS
TEST CONDITIONS
F49L160UA/F49L160BA
Figure 3. Test Setup
2.7K
DEVICE UNDER TEST
+3.3V
CL
6 .2 K
DIODES = IN 3064 O R EQ U I V A L E N T
C L = 1 0 0 p F I n c lu d i n g ji g c a p a c it a n c e C L = 3 0 p F f o r F4 9 L 8 0 0 U/ BA
Figure 4. Input Waveforms and Measurement Levels
3.0V 0V 1.5V In p u t Test Poin t s Out pu t
1.5V
A C TE S TIN G : In p u t s a r e d ri v e n a t 3 . 0 V f o r a l o g i c " 1 " a n d 0 V f o r a l o g i c " 0 " In p u t p u l s e r i s e a n d f a l l t i m e s a r e < 5 n s .
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10.1 Read Operation TA = 0C to 70C, VCC = 2.7V~3.6V
F49L160UA/F49L160BA
Table 14. Read Operations Symbol tRC tACC tCE tOE tDF Description Read Cycle Time (Note 1) Address to Output Delay
CE to Output Delay CE = OE = VIL
Conditions
-70 Min. 70 Max. 70 70 30 16 0 10 0 10 0 Min. 90
-90 Max. 90 90 35 30
Unit ns ns ns ns ns ns ns ns
OE = VIL
CE = VIL CE = VIL
OE to Output Delay OE High to Output Float (Note1)
Output Enable Read Toggle and Data Polling
tOEH tOH
Hold Time
Address to Output hold
CE = OE = VIL
0
Notes :
1. Not 100% tested. 2. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven.
Figure 5. Read Timing Waveform
tRC Addr es s Addresses Stabl e tAC C CE
tOE OE tOEH WE tCE tOH Ou t pu t s High-Z
tDF
High-Z Output Vali d
RESET
RY/BY
0V
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10.2 Program/Erase Operation
-70 Min. 70 0 45 35 0 0 0 0 0 35 30 Byte Word 9(typ.) 11(typ.) 0.7(typ.) 50 0 90
F49L160UA/F49L160BA
Table 15. WE Controlled Program/Erase Operations(TA = 0C to 70C, VCC = 2.7V~3.6V) Symbol tWC tAS tAH tDS tDH tOES tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS tRB tbusy Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write ( OE High to WE low)
CE Setup Time CE Hold Time
-90 Max. Min. 90 0 45 45 0 0 0 0 0 35 30 9(typ.) 11(typ.) 0.7(typ.) 50 0 90 Max.
Unit ns ns ns ns ns ns ns ns ns ns ns us sec us ns ns
Write Pulse Width Write Pulse Width High Programming Operation (Note 2)
Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Recovery Time from RY/ BY Program/Erase Valid to RY/ BY Delay
Notes : 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information.
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F49L160UA/F49L160BA
Table 16. CE Controlled Program/Erase Operations(TA = 0C to 70C, VCC = 2.7V~3.6V) Symbol tWC tAS tAH tDS tDH tOES tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 Notes : 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write
WE Setup Time WE Hold Time
CE Pulse Width CE Pulse Width High
-70 Min. 70 0 45 35 0 0 0 0 0 35 30 Byte Word 9(typ.) 11(typ.) 0.7(typ.) Max.
-90 Min. 90 0 45 45 0 0 0 0 0 35 30 9(typ.) 11(typ.) 0.7(typ.) Max. Unit ns ns ns ns ns ns ns ns ns ns ns us us sec
Programming Operation(note2)
Sector Erase Operation (note2)
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VCC
F49L160UA/F49L160BA
Figure 6. Write Command Timing Waveform
3V
Addr es s
VIH VIL tAS VIH
ADD Valid tAH
WE
VIL tOES tWP tCW C tWPH
CE
VIH VIL tCS tCH VIH VIL tDS tDH DIN
OE
Dat a
VIH VIL
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F49L160UA/F49L160BA
Figure 7. Embedded Programming Timing Waveform
Pr ogr am C omm an d S equ en ce ( l as t t wo cycl e)
Read Stat us D at a ( last t w o cycl e)
tWC Addr es s 5 55 h
tAS PA tAH PA PA
CE tGHWL tCH
OE tW HW H1
tWP WE tCS tDS tDH A0 h PD tB US Y tWPH
Dat a
St at u s
DOUT
tRB
RY/BY tVCS
VCC
Notes : 1. PA = Program Address, PD = Program Data, DOUT is the true data the program address.
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F49L160UA/F49L160BA
Figure 8. Embedded Programming Algorithm Flowchart
Start
W rite Data AAH Address 555H
W rite Data 55H Address 2AAH
W rite Data A0H Address 555H
In c r e m e n t address
W rite Program Data/Address
Data Poll from system
No
Verify W ork OK? Ye s
No
Last address? Ye s
Embedded Program Completed
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555 for prog ram PA f or p rog r am 2AA for erase SA for sector erase 555 for ch ip eras e
F49L160UA/F49L160BA
Figure 9. CE Controlled Program Timing Waveform
Data Pol li n g PA
Addr es s tWC tWH WE tG HEL tAS tAH
OE tCP tWHWH1 CE tWS tDS tDH Dat a
A0 f o r p r og r a m PD f o r p r o g r a m 30 f or sect or erase 55 for erase 10 f or ch ip erase or 2
tCPH
tBUSY
DQ7 DOUT
tRH RESET
RY/BY
Notes : 1. PA = Program Address, PD = Program Data, DOUT = Data Out , DQ7 = complement of data written to device 2. Figure indicates the last two bus cycles of the command sequence..
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Er as e Com mand Sequ en ce( last t w o cycl e)
F49L160UA/F49L160BA
Figure 10. Embedded Chip Erase Timing Waveform
Read Statu s Dat a
tWC Addr es s 2AAh
tAS 5 55 h tAH VA VA
CE tCH tGHWL
OE
tWP WE tCS tDS tDH 5 5h 1 0h tBUSY tWPH
tW HW H2
Dat a
In Progress Complete
tRB
RY/BY tVCS VCC
Notes : SA = Sector Address (for Sector Erase, VA = Valid Address for reading status data (see "Write Operation Status")
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F49L160UA/F49L160BA
Figure 11. Embedded Chip Erase Algorithm Flowchart
Start
W rite Data AAH Address 555H
W rite Data 55H Address 2AAH
W rite Data 80H Address 555H
W rite Data AAH Address 555H
W rite Data 55H Address 2AAH
W rite Data 10H Address 555H
Data Poll from System
No
Data = FFh? Ye s
Embedded Chip Erease Completed
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F49L160UA/F49L160BA
Figure 12. Embedded Sector Erase Timing Waveform
Er as e Com mand Sequ en ce( last t w o cycl e)
Read Statu s Dat a
tWC Addr es s 2AAh
tAS SA tAH VA VA
CE tCH tGHWL
OE
tWP WE tCS tDS tDH 55 h 3 0h tBUSY tWPH
tW HW H2
Dat a
In Progress Complete
tRB
RY/BY tVCS VCC
Notes : SA = Sector Address (for Sector Erase, VA = Valid Address for reading status data (see "Write Operation Status")
Elite Semiconductor Memory Technology Inc.
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Start
F49L160UA/F49L160BA
Figure 13. Embedded Sector Erase Algorithm Flowchart
W rite Data AAH Address 5 55H
W rite Data 55 H Address 2AAH
W rite Data 80H Address 555H
W rite Data AAH Add ress 555H
W rit e Data 55H Address 2AAH
W rite Data 3 0H Address SA
Last Sector to Erase Yes Data Po ll fro m System
No
No Data = FFH?
Embedde d Sector Ere ase Co mplete d
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F49L160UA/F49L160BA
Figure 14. Erase Suspend/Erase Resume Flowchart
Start
W rite Data B0H ERASE SUSPEND
Tog gle Bi t c h ec kin g Q 6 not toggled
No
Ye s Read Array or Program
Readi ng or Pr og r am m in g En d
No
Ye s W rite Data 30H ERASE RESUME
Continue Erase
An oth er Er ase Suspend?
No
Ye s
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F49L160UA/F49L160BA
Figure 15. In-System Sector Protect/Unprotect Timing Waveform ( RESET Control)
VID VIH RESET
SA,A 6 A1,A0
Valid* Sec t or P r ot ec t Sec tor U npr ot ec t
Valid* Ver if y 4 0h
Sector Protect = 150us Sec t or Un p r ot ect = 15m s
Vali d*
Dat a 1us
60 h
6 0h
St at u s
CE
WE
OE
Notes : When sector protect, A6=0, A1=1, A0=0. When sector unprotect, A6=1, A1=1, A0=0.
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F49L160UA/F49L160BA
Figure 16. In-System Sector Protect/Unprotect Algorithm ( RESET = VID)
Start
Start
PLSCNT = 1 Protect all sector : The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
PLSCNT = 1
RESET = VID
RESET = VID
W ait 1 s?
W ait 1 s?
Temporary Sector Unprotect Mode
No
First W rite Cyc le = 6 0 h ?
First W rite Cyc le = 6 0 h ?
No
Temporary Sector Unprotect Mode
Ye s Set up sector address No
Ye s
Al l s ec t o r s pr otected?
Sector Protect : W rite 60h to sector address with A6 = 0, A1 = 1, A0 = 0
Ye s Set up first sector address
W ait 150 s?
Sector Unprotect : W rite 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Reset PLSCNT = 1
In c r e m e n t PL SC NT
Verify Sector Protect : W rite 40h to sector address with A6 = 0, A1 = 1, A0 = 0
W ait 15 ms?
Read from sector address with A6 = 0, A1 = 1, A0 = 0 No PLSCNT = 25? No Data = 01h? Ye s Protect another s e c to r ? No Remove VID from RESET Ye s
In c r e m e n t PL SC NT
Verify Sector Unprotect : W rite 40h to sector address with A6 = 1, A1 = 1, A0 =0
Ye s Dev ice failed
Read from sector address with A6 = 1, A1 = 1, A0 =0 No PLSCNT = 1000? Ye s Dev ice failed No Data = 00h? Set up next sector address
Ye s Last sector v erified ? Ye s No
W rite reset command
Sector Protect Algorithm
Sector Protect c o m p le te
Sector Unprotect Algorithm
Remove VID from RESET
W rite reset command
Sector Protect c o m p le te
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F49L160UA/F49L160BA
Figure 17. Sector Protect Timing Waveform (A9, OE Control)
A0,A1
A6
12 V 3V
A9 tVLHT
12 V 3V
Ver if y OE tVLHT tWPP1 tVLHT
WE tOESP CE
Dat a tOE A1 8~ A1 2 Sec to r Ad dr es s
01H
F0H
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ESMT
Start
F49L160UA/F49L160BA
Figure 18. Sector Protection Algorithm (A9, OE Control)
Set up sector address
PLSCNT = 1
OE = VID, A9 = VID, CE = VIL A6 = VIL
Activ ate W E Pluse
Time out 150us
Set W E = VIH , CE = OE = VIL A9 should remain VID
No No PLSCNT = 32? Ye s Dev ice Failed
Read from Sector Address = SA, A0=1, A1 = 1
Data = 01H?
Protect Another Sector?
Ye s
Remov e VID from A9 W rite reset command Sector Protection C o m p l e te
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F49L160UA/F49L160BA
WRITE OPERATION STATUS
Figure 19. Data Polling Algorithm
Start Read DQ7~DQ0 Add. = VA(1)
DQ7 = Data?
Ye s
No No
D Q5 = 1?
Ye s Read DQ7~DQ0 Add. = VA
DQ7 = Data?
Ye s (2 )
No FAIL Pass
Notes : 1. VA =Valid address for programming. 2. DQ7 should be re-checked even DQ5 = "1" because DQ7 may change simultaneously with DQ5.
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Start
F49L160UA/F49L160BA
Figure 20. Toggle Bit Algorithm
Read DQ7 ~ DQ0
Read DQ7 ~ DQ0
(Note 1)
Toggle Bit = DQ6 Toggle?
No
Ye s No
D Q 5 = 1?
Ye s
Re ad D Q7 ~D Q 0 Tw ice
(Note 1,2)
Toggle bit D Q6 = Tog gle?
No
Ye s Program / Erase operation Not complete, write reset command Program / Erase operation complete
Note : 1. Read toggle bit twice to determine whether or not it is toggle. 2. Recheck toggle bit because it may stop toggling as DQ5 change to "1".
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F49L160UA/F49L160BA
Figure 21. Data Polling Timings (During Embedded Algorithms)
tRC Addr es s tAC C tCE CE tCH tOE OE tOEH tDF VA VA
WE tO H High-Z DQ7
Complement Complement Tr u e Vai l d Dat a
High-Z DQ0~DQ6 tB US Y
Statu s Data Statu s Data Tr u e Vai l d Dat a
RY/BY
Notes : VA = Valid Address. Figure shows first status cycle after command sequence, last status read cycle, and array data read cycle.
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tRC Ad dr es s VA tAC C tCE CE tCH tOE OE tOEH tDF VA
F49L160UA/F49L160BA
Figure 22. Toggle Bit Timing Waveforms (During Embedded Algorithms)
VA
VA
WE tOH DQ6/DQ2 High-Z tBUSY
Vaild Status Vaild Status
Vaild Data (stops tog gling )
Vaild Data
(fi rst re ad )
(sec ond read )
RY/BY
Notes : VA = Valid Address; not required for DQ6. Figure shows first status cycle after command sequence, last status read cycle, and array data read cycle.
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10.3 Hardware Reset Operation
F49L160UA/F49L160BA
Table 17. AC CHARACTERISTICS Symbol TREADY1 TREADY2 TRP TRH TRB Description
RESET Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) RESET Pulse Width (During Embedded Algorithms) RESET High Time Before Read(See Note)
All Speed Options Max Max Min Min Min 20 500 500 50 0
Unit us ns ns ns ns
RY/ BY Recovery Time(to CE , OE go low)
Notes : Not 100% tested
Figure 23. RESET Timing Waveform
RY/BY
CE, O E tRH RESET tRP tRead y2
Reset T i mi ng NO T dur i ng Au tom at i c Al gor i th m s tRead y1
RY/BY tRB CE, O E
RESET tRP Reset Tim ing during Automatic Algorithm s
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10.4 TEMPORARY SECTOR UNPROTECT Operation
F49L160UA/F49L160BA
Table 18. Temporary Sector Unprotect
Symbol TVIDR TRSP Notes: Not 100% tested Description VID Rise and Fall Time (See Note)
RESET Setup Unprotect
All Speed Options Min Sector Min 500 4
Unit ns us
Time
for
Temporary
Figure 24. Temporary Sector Unprotect Timing Diagram
12V RESET 0 or VCC tVIDR CE
Program or Er ase Com man d Seq uence
0 or VCC tVIDR
WE tRSP RY/BY
Figure 25. Q6 vs Q2 for Erase and Erase Suspend Operations
En ter E m bedde d Er as in g WE Er as e S u s pe n d Enter Eras e Suspend Program Er as e Su s pen d Pr ogr am Er as e Resume Er as e Su s pen d Read Er as e Er as e Com pl et e
DQ6
DQ2
Notes : The system can use OE or CE to toggle DQ2 / DQ6, DQ2 toggles only when read at an address within an erase-suspended.
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F49L160UA/F49L160BA
Figure 26. Temporary Sector Unprotect Algorithm
Start
RESET = VID (Note 1)
Program Erase or Program Operation
Operation Completed
RESET = VIH
Temporary Sector Unprotect Completed (Note 2)
Notes : 1. All protected status are temporary unprotect. VID = 10V~10.5V 2. All previously protected sectors are protected again.
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F49L160UA/F49L160BA
Figure 27. ID Code Read Timing Waveform
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11. ERASE AND PROGRAMMING PERFORMANCE
F49L160UA/F49L160BA
Table 19. Erase And Programming Performance (Note.1)
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Chip Programming Time Erase/Program Cycles (1) Data Retention Notes: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25C, 3.3V. 3.Maximum values measured at 85C, 2.7V. Byte Mode Word Mode Limits Typ.(2) 0.7 15 9 11 18 12 100,000 20 Max.(3) 15 30 300 360 54 36 Unit Sec Sec Us Us Sec Sec Cycles Years
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12. PACKAGE DIMENSION 48-LEAD TSOP(I) ( 12x20 mm )
F49L160UA/F49L160BA
Symbol A A1 A2 b b1 c c1
Dimension in mm Min Norm Max ------- ------- 1.20 0.05 ------- 0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.17 0.10 0.10 0.20 ------------0.23 0.21 0.16
Dimension in inch Dimension in mm Symbol Min Norm Max Min Norm Max D ------- ------- 0.047 20.00 BSC 0.006 ------- 0.002 D1 18.40 BSC 0.037 0.039 0.041 E 12.00 BSC 0.007 0.009 0.011 0.50 BSC e L 0.007 0.008 0.009 0.50 0.60 0.70 0.004 0.004 ------------0.008 0.006 0
O
Dimension in inch Min Norm Max 0.787 BSC 0.724 BSC 0.472 BSC 0.020 BSC 0.020 0O 0.024 ------0.028 8O
-------
8
O
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All rights reserved.
F49L160UA/F49L160BA
Important Notice
No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of EFST. The contents contained in this document are believed to be accurate at the time of publication. EFST assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by EFST for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of EFST or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. EFST 's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.
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